The Computer Engineering HandbookVojin G. Oklobdzija CRC Press, 2001 M12 26 - 1408 pages There is arguably no field in greater need of a comprehensive handbook than computer engineering. The unparalleled rate of technological advancement, the explosion of computer applications, and the now-in-progress migration to a wireless world have made it difficult for engineers to keep up with all the developments in specialties outside their own. References published only a few years ago are now sorely out of date. The Computer Engineering Handbook changes all of that. Under the leadership of Vojin Oklobdzija and a stellar editorial board, some of the industry's foremost experts have joined forces to create what promises to be the definitive resource for computer design and engineering. Instead of focusing on basic, introductory material, it forms a comprehensive, state-of-the-art review of the field's most recent achievements, outstanding issues, and future directions. The world of computer engineering is vast and evolving so rapidly that what is cutting-edge today may be obsolete in a few months. While exploring the new developments, trends, and future directions of the field, The Computer Engineering Handbook captures what is fundamental and of lasting value. |
Contents
Fabrication and Technology | 1-1 |
Trends and Projections for the Future of Scaling and Future Integration Trends | 1-3 |
CMOS Circuits | 2-3 |
HighSpeed LowPower Emitter Coupled Logic Circuits | 3-3 |
PricePerformance of Computer Technology | 4-3 |
Computer Systems and Architecture | 5-1 |
Computer Architecture and Design | 5-3 |
System Design | 6-3 |
DSP Applications | 25-3 |
Digital Filter Design | 26-3 |
Audio Signal Processing | 27-3 |
Digital Video Processing | 28-3 |
LowPower Digital Signal Processing | 29-3 |
Communications and Networks | 30-1 |
Communications and Computer Networks | 30-3 |
InputOutput | 31-1 |
Architectures for Low Power | 7-3 |
Performance Evaluation | 8-3 |
Computer Arithmetic | 9-3 |
Design Techniques | 10-1 |
Timing and Clocking | 10-3 |
MultipleValued Logic Circuits | 11-3 |
FPGAs for Rapid Prototyping | 12-3 |
Issues in HighFrequency Processor Design | 13-3 |
Design for Low Power | 14-1 |
LowPower Design Issues | 14-3 |
LowPower Circuit Technologies | 15-3 |
Dynamic Voltage Scaling | 17-3 |
LowPower Design of Systems on Chip | 18-3 |
ImplementationLevel Impact on LowPower Design | 19-3 |
Accurate Power Estimation of Combinational CMOS Digital Circuits | 20-3 |
ClockPowered CMOS for EnergyEfficient Computing | 21-3 |
Embedded Applications | 22-1 |
Embedded SystemsonChips | 22-3 |
Embedded Processor Applications | 23-3 |
Signal Processing | 24-1 |
Digital Signal Processing | 24-3 |
Circuits for HighPerformance IO | 31-3 |
Algorithms and Data Structures in External Memory | 32-3 |
Parallel IO Systems | 33-3 |
A Read Channel for Magnetic Recording | 34-3 |
Operating System | 35-1 |
Distributed Operating Systems | 35-3 |
New Directions in Computing | 36-1 |
SPS A Strategically Programmable System | 36-3 |
Reconfigurable Processors | 37-3 |
Roles of Software Technology in Intelligent Transportation Systems | 38-3 |
Media Signal Processing | 39-3 |
Internet Architectures | 40-3 |
Microelectronics for Home Entertainment | 41-3 |
Mobile and Wireless Computing | 42-3 |
Data Security | 43-3 |
Testing and Design for Testability | 44-1 |
SystemonChip SoC Testing Current Practices and Challenges for Tomorrow | 44-3 |
Testing of Synchronous Sequential Digital Circuits | 45-3 |
Scan Testing | 46-3 |
ComputerAided Analysis and Forecast of Integrated Circuit Yield | 47-3 |
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Common terms and phrases
adder algorithm applications architecture audio B-trees bandwidth benchmarks block branch branch prediction cache capacitance cell chip clock clock-powered CMOS components Computer cycle decoder delay depends devices disk drive dynamic efficient embedded execution fetch FIGURE filter flip-flop FPGA frequency full adder function gate hardware IEEE implementation increase input instruction Intel interconnect interface inverter jitter latch leakage current load logic logic gates loop low-power memory microprocessor MOSFETs multiple NMOS noise operands operation optimal output parallel parameters pass-transistor path performance phase pipeline PMOS transistor power consumption precharged prediction predictor problem Proc processor reduced register file register renaming rename buffers result sampling server shown in Fig signal processing simulation Solid-State Circuits speed static structure substrate subthreshold leakage superscalar supply voltage switching techniques threads threshold voltage transistor typically VCDL vector VLIW VLSI